從RTL到GDS的功耗優(yōu)化全流程
2022年電子技術(shù)應(yīng)用第8期
顧東華1，曾智勇1，余金金1，黃徐輝1，朱嘉駿2，何湘君2，陳澤發(fā)2
1.燧原科技上海有限公司，上海200000；2.上海楷登電子科技有限公司，上海200000
摘要： 功耗作為大型SoC芯片的性能功耗面積(PPA)三要素之一，已經(jīng)變得越來(lái)越重要。尤其是當(dāng)主流設(shè)計(jì)平臺(tái)已經(jīng)發(fā)展到了7 nm以下。AI芯片一般會(huì)有多個(gè)核心并行執(zhí)行高性能計(jì)算任務(wù)。這種行為會(huì)產(chǎn)生巨大的功耗。因此在AI芯片的設(shè)計(jì)過程中，功耗優(yōu)化變得尤為重要。利用一個(gè)典型的功耗用例波形或者一組波形，可以從RTL進(jìn)來(lái)開始功耗優(yōu)化。基本的方式是借助Joules-replay實(shí)現(xiàn)基于RTL波形產(chǎn)生相對(duì)應(yīng)的網(wǎng)表波形。在Genus的syn-gen、syn-map、syn-opt三個(gè)綜合階段，都可以加入Joules-replay，并且產(chǎn)生和綜合網(wǎng)表相對(duì)應(yīng)的波形，用于Innovus PR階段進(jìn)一步地進(jìn)行功耗優(yōu)化。在Innovus中實(shí)現(xiàn)Place和Routing也分為3個(gè)階段：place_opt、cts_opt和route_opt。同樣每一步都可以引入Joules-replay來(lái)生成功耗優(yōu)化所需的網(wǎng)表波形。最終在Tempus timing signoff的環(huán)境中，再次引入波形進(jìn)行功耗優(yōu)化。基于上面的一系列各個(gè)節(jié)點(diǎn)的精確功耗優(yōu)化該設(shè)計(jì)可以獲得10%以上的功耗節(jié)省。此時(shí)再結(jié)合multi-bit技術(shù)，最終可以獲得21%的功耗節(jié)省。
中圖分類號(hào)： TN402
文獻(xiàn)標(biāo)識(shí)碼： A
DOI：10.16157/j.issn.0258-7998.229807
中文引用格式： 顧東華，曾智勇，余金金，等. 從RTL到GDS的功耗優(yōu)化全流程[J].電子技術(shù)應(yīng)用，2022，48(8)：65-69.
英文引用格式： Gu Donghua，Zeng Zhiyong，Yu Jinjin，et al. Fully power optimization flow from RTL to GDS[J]. Application of Electronic Technique，2022，48(8)：65-69.
文獻(xiàn)標(biāo)識(shí)碼： A
DOI：10.16157/j.issn.0258-7998.229807
中文引用格式： 顧東華，曾智勇，余金金，等. 從RTL到GDS的功耗優(yōu)化全流程[J].電子技術(shù)應(yīng)用，2022，48(8)：65-69.
英文引用格式： Gu Donghua，Zeng Zhiyong，Yu Jinjin，et al. Fully power optimization flow from RTL to GDS[J]. Application of Electronic Technique，2022，48(8)：65-69.
Fully power optimization flow from RTL to GDS
Gu Donghua1，Zeng Zhiyong1，Yu Jinjin1，Huang Xuhui1，Zhu Jiajun2，He Xiangjun2，Chen Zefa2
1.Enflame Technology，Shanghai 200000，China；2.Cadence Design System，Inc.，Shanghai 200000，China
Abstract： Power as one part of PPA(Performance, Power and Area) becomes more and more important in large SoC chips, especially under 7 nm technology. AI chips schedule multi-cores in parallel for specific application scenario, which lead to very large power consumption. Power optimization for each core is highest priority for an AI chip design. With a typical power scenario or multi-scenario grouped together, we can do power optimization from RTL synthesis to GDS. The basic flow is using Joules-replay to convert RTL activity file(time-based formats-VCD/FSDB/SHM/PHY) to gate level activity file. Synthesis with Genus has 3 steps: syn-gen, syn-map and syn-opt, Joules-replay is added after each step, and the replayed activity file will be used in power optimization in next step, which increase power estimation accuracy. Innovus place and route also has 3 main steps: place-opt, CTS-opt and route-opt, same flow with Joules-replay can be involved after each step, and it generates stimulus activity for next step. At final timing signoff stage, we use post-sim activity for power opt in Tempus. With this full flow power optimization flow, we can achieve more than 10% power reduction, combined with MBFF(Multi-Bit Flip-Flop) optimization, we can get 21% power reduction finally.
Key words : power optimization；AI chip design；SoC physical design；Joules-replay；Genus；Innovus
0 引言
芯片設(shè)計(jì)一直在追求最好的PPA，在28 nm之前的技術(shù)節(jié)點(diǎn)上，很多時(shí)候更多地優(yōu)先考慮性能和面積。隨著技術(shù)節(jié)點(diǎn)向7 nm進(jìn)化，標(biāo)準(zhǔn)單元的密度不斷提升，隨之而來(lái)的功耗密度也越來(lái)越大。因此作為PPA之一的功耗在設(shè)計(jì)中變得尤為重要。設(shè)計(jì)芯片需要在流程的各個(gè)節(jié)點(diǎn)盡量對(duì)功耗進(jìn)行精確評(píng)估并進(jìn)行優(yōu)化，否則最終芯片的性能很可能由于功耗過大而無(wú)法充分發(fā)揮。
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作者信息：
顧東華1，曾智勇1，余金金1，黃徐輝1，朱嘉駿2，何湘君2，陳澤發(fā)2
(1.燧原科技上海有限公司，上海200000；2.上海楷登電子科技有限公司，上海200000)
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