中圖分類號：TN92 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.245160 中文引用格式： 張恒，王琪，郁文君. 一種PCIe轉(zhuǎn)RapidIO擴展卡設(shè)計與實現(xiàn)[J]. 電子技術(shù)應(yīng)用，2024，50(10)：110-114. 英文引用格式： Zhang Heng，Wang Qi，Yu Wenjun. Design and implementation of a PCIe-to-RapidIO add-in card[J]. Application of Electronic Technique，2024，50(10)：110-114.
Design and implementation of a PCIe-to-RapidIO add-in card
Zhang Heng，Wang Qi，Yu Wenjun
The 58th Research Institute of China Electronics Technology Group
Abstract： RapidIO bus is a high-performance interconnect bus which is widely used in embedded systems. It has the characteristics of high bandwidth, low latency, and multiple processors supported. In response to the problem that most processors on the market currently don’t support the RapidIO bus, a PCIe add-in card based on domestic PCIe to RapidIO controller was designed. The hardware design of each module of the PCIe add-in card was introduced in detail, and a testing environment was built to test the eye diagram and DMA transmission rate of the RapidIO bus. By testing, when the transfer rate of the RapidIO bus is configured as 5 Gb/s, the DMA read and DMA write rates of the RapidIO bus are 1 677 MB/s and 1 711 MB/s, respectively.
Key words : RapidIO bus；PCIe；PCIe to RapidIO controller；eye diagram；DMA transmission
